Progressive scan television receivers have been proposed wherein the horizontal scan rate is doubled and each line of video is displayed twice thereby providing a displayed image having twice the usual number of scan lines and thus reduced visibility of vertical line structure. In a typical progressive scan receiver each incoming horizontal line of video signal is stored in one of two memories. As one line is being stored in one memory, the line previously stored in the other memory is recovered or "read" twice thereby providing two lines of time compressed video within one standard line interval. The memory output is applied to a display having a doubled horizontal sweep rate synchronized with read-out of the memory thereby doubling the number of displayed lines of video signal.
An example of a progressive scan receiver in which the additional scan lines added to the display are obtained by interpolation from the original scan lines is described by K. H. Powers in U.S. Pat. No. 4,400,719 entitled TELEVISION DISPLAY SYSTEM WITH REDUCED LINE-SCAN ARTIFACTS which issued Aug. 23, 1983. A receiver in which the added lines are replicas of the original lines is described by R.A. Dischert in U.S. Pat. No. 4,415,931 entitled TELEVISION DISPLAY WITH DOUBLED HORIZONTAL LINES which issued Nov. 15, 1983. The arrangements disclosed in these patents are incorporated by reference herein.
When implementing progressive scanning in a receiver with digital signal processing circuits, one may employ random access memories (RAM) for the line stores. Digital signal processing typically utilizes a coherent clock for purposes such as signal sampling (in the A/D converter), memory address control and other functions. For simplicity of chroma processing (e.g., decoding) it is advantageous to phase lock the clock to an integer multiple of the color subcarrier frequency. For NTSC standard video signals the memory write clock frequency is typically selected to be four-times that of the color subcarrier (4 Fsc) or about 14.3 MHz with a period of about 70 nanoseconds. One line of memory, for this clock frequency and the standard NTSC line period of about 63.5 microseconds, therefore requries 910 locations (addresses) in RAM to store 910 video samples or picture elements ("pixels" hereinafter). This memory requirement is invarient for NTSC standard signals because under the NTSC standard there are exactly 227.5 color subcarrier cycles per horozontal line. With D/A conversion done at four-times the color subcarrier frequency there are thus exactly 910 pixels per line (4.times.227.5). As long as the memory read clock is exactly double the frequency of the write clock, the result and "double-speed" or "time-compressed" pixels will have proper horizontal spacing and vertical alignment when displayed.
A problem exists is progressive scan systems of the type described (which employ "burst locked" clocks) when processing for display what will be referred to hereinafter as "non-standard" video input signals. As used herein, the term non-standard refers to video input signals wherein the ratio of the color subcarrier frequency to the horizontal line frequency does not conform exactly to a specified broadcasting standard (e.g., 227.5 in the NTSC standard). Where, for example, the video source is a video disc player, a video casette recorder, a video game unit or some other non-standard source, the burst/line-frequency ratio may vary continuously within certain limits. These limits may include a significant variztion from the standard ratio over a range of values. Under these conditions, the number of video samples (pixels) in a horizontal line period will not, in general, be an integer (e.g., 910). The number of 4 Fsc clock periods contained within one horizontal line period, in other words, may differ from the standard and this difference may include a fractional part of one clock cycle.
The deviation of the number of pixels per line from the standard value (e.g., 910) can result in a precession of the memory clock phase with respect to the incoming horizontal synchronizing signal phase. The effect of this precession or "phase-slip" or "skew" is that horizontal timing errors accumulate throughout each field scan interval. Moreover, the memory read clock precession relative to the double line-rate deflection will be twice as great as the precession of the memory write clock relative to the normal line-rate incoming video signal. This problem can cause accumulated horizontal timing errors which can result in full pixel discontinuities between occassional lines and other undesirable visible artifacts such as picture skew and ragged edges.
The need for skew correction of non-standard signals in a progressive scan processor employing a burst-locked clock has been recognized by Willis, et al. in U.S. Pat. Application Ser. No. 615,423 entitled PROGRESSIVE SCAN TELEVISION RECEIVER FOR NON-STANDARD SIGNALS filed May 29, 1984, now U.S. Pat. No. 4,593,315. In the Willis et al. system means are provided for measuring the phase of the speed-up memory read and write clocks with respect to the horizontal sweep of the display. Skew correction is provided by delaying the video signal recovered from the speed-up memory as a function of the difference between the read and write clock skew measurements each time the memory is read.